Latency between 2 signals

SystemVerilog
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2

In reply to verif4ravi:


property p_min_time();
  realtime start_time;
  @(posedge sig1) (1,start_time = $realtime) |->
  @(posedge sig2) (($realtime - start_time) == duration);
endproperty

ap_min_time: assert property p_min_time;