Large number of cover property

SystemVerilog
1

I’m creating a coverage for signals timing skew.
I’m using cover property to account for timing skew of 0, 1, 2 clock cycles between two signals. (Let say 3 cover property here)
Then I created a excel sheet with 3 coverage requirements.
The Questasim generated ucdb coverage will link to the excel sheet and a html report will show the details of the coverage.

define skew(signal_req, signal_ack, delay, clk=clkin, rst_n=rstin_n) \ cover property (@(posedge clk) disable iff (!rst_n) $rose(signal_ack) |-> ##delay $fell(signal_req));* * SKEW_COV: skew(aa_req, aa_ack, 0);
skew(aa_req, aa_ack, 1); skew(aa_req, aa_ack, 2);

The above flow apply for small set of signals.
I’m trying to create coverage for large group of signals (aa to zz). The problem with the above flow is with the growing number of cover property, I need to create a lot more coverage requirements in the excel sheet. I’m also susceptible to missing a few cover property or coverage requirement.

Is there any recommended coding style or strategy to eliminate the risk of missing cover property or coverage requirement?

2

I suggest you approach it differently.

  1. Use property with formal argument (and pass aa_req, aa_ack, delay as arguments)
  2. See if you can map your aa_req, bb_req etc. to an array of signal. Then it becomes easier to automate
  3. Use generate around the cover property

We did similar stuff for “per-bit-coverage” of a slave-select for customer earlier. It works nicely.

If you get stuck at some code, post them here to seek additional help.

Good Luck
Ajeetha, CVC

3

Thanks! It works greatly.