Hi,
I have an environment where I have integrated AXI VIP.I have also added a “my_component” class which is extended from uvm_component in my environment.so,what we did is we were sending some register values from test in order to do read write operation in “my_component” class through AXI VIP.whatever register values we were sending from test it is entering into AXI Environment successfully and we were also receiving the value in test.But the problem is it is not entering into the “my_component” class.whenever I try to call the read and write operation of “my_component” class from AXI slave sequence it is throwing error like NULL OBJECT ACCESS in slave sequence.But if that same “my_component” class is not extended from uvm_component rather when it is taken as a class and its handle is instantiated in the same slave sequence then it easily passes into the “my_component” class.
Error-[NOA] Null object access
slave_reg_response_sequence.sv, 141
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Kindly suggest me some ways to overcome this steps
This is the sequence code ,Kindly have a look into the comment which I have written at initial stage and please tell me how to access the hci_read and write function of hci class from this axi sequence.
code :
typedef class host_controller_reg_memory;//This is simply a class whose function I want to call from this sequence at line no 53.Here when i created a new constructor read and write function of this class is working fine.Now I have changed "host_controller_reg_memory" class to a component class which was previously simply a class.After changing it to component class when I tried to access hci.write_function(req_resp) at line no.53 it is throwing error which was not previously shown when it was simply a class
class slave_reg_response_sequence extends axi_slave_base_sequence;
axi_slave_transaction req_resp;
/** UVM Object Utility macro */
`uvm_object_utils(slave_reg_response_sequence)
host_controller_reg_memory hci;
/** Class Constructor */
function new(string name="slave_reg_response_sequence");
super.new(name);
hci=new();
endfunction
//Body where read and write function are called
virtual task body();
integer status;
configuration get_cfg;
`uvm_info("body", "Entered ...", UVM_LOW)
p_sequencer.get_cfg(get_cfg);
if (!$cast(cfg, get_cfg)) begin
`uvm_fatal("body", "Unable to $cast the configuration to a svt_axi_port_configuration class");
end
// consumes responses sent by driver
sink_responses();
forever begin
/**
* Get the response request from the slave sequencer. The response request is
* provided to the slave sequencer by the slave port monitor, through
* TLM port.
*/
p_sequencer.response_request_port.peek(req_resp);
status=req_resp.randomize with {
bresp == axi_slave_transaction::OKAY;
foreach (rresp[index]) {
rresp[index] == axi_slave_transaction::OKAY;
}
};
if(req_resp.get_transmitted_channel() == axi_slave_transaction::WRITE) begin
hci.write_function(req_resp);
end
else if (req_resp.get_transmitted_channel() == axi_slave_transaction::READ) begin
hci.read_function(req_resp);
end
$cast(req,req_resp);
`uvm_send(req)
end
`uvm_info("body", "Exiting...", UVM_LOW)
endtask: body
endclass
ISSUE:HERE read write is successfully working as host_controller_reg_memory is a class.
But when the below thing is done,it throws error
class host_controller_reg_memory extends uvm_component;
error:[ILLCRT] It is illegal to create a component (‘host_controller_reg_memory’ under ‘’) after the build phase has ended.
Kindly suggest me ways to access the read and write function of class host_controller_reg_memory.
Thanks in advance.
In reply to chr_sue:
hci.read_function(req_resp);//This is line no.141
This “NULL OBJECT ACCESS” error occurs at line no.141 after some modification in the above sequences.A class “slave_mem” is there in AXI_VIP which is used for read and write purposes in slave memory.
slave_mem mem_h;
/** Class Constructor */
function new(string name=“slave_reg_response_sequence”);
super.new(name);
mem_h =slave_mem::type_id::create(“mem_h”);
endfunction
I think , since you are using UVM_COMPONENT, that must be part of hierarchy (created in build_phase), can you tell me exactly you are creating this component ?
In reply to chr_sue:
hci.read_function(req_resp);//This is line no.141
This “NULL OBJECT ACCESS” error occurs at line no.141 after some modification in the above sequences.A class “slave_mem” is there in AXI_VIP which is used for read and write purposes in slave memory.
slave_mem mem_h;
/** Class Constructor */
function new(string name=“slave_reg_response_sequence”);
super.new(name);
mem_h =slave_mem::type_id::create(“mem_h”);
endfunction
I assume host_controller_reg_memory is your RAL model. Correct? Then it is not an extension of uvm_component and it does not belong to your testbench hierarchy. Instead it is an extension of uvm_object. It has been created already and you have to connect this hanle in your sequence to the hanld of the RAL model in one of your components. Commonly this handle is available in the uvm_env.
*What you said is partially correct,The host_controller_reg_memory class which i have taken is not actually RAL MODEL,you can say a register class which contains all the register which we require in order to run our vip.This class is fully responsible for all VIP operation.
*second thing, host_controller_reg_memory class i have extended from uvm_component.
class host_controller_reg_memory extends uvm_component;
*so,it is a separate entity inside our testbench as it has been created inside environment,inside our environment we have this class as well as AXI_VIP created.That class itself is an environment you can say,but without driver and sequencer.
*Now through the sequence which I have mentioned I was trying to pass handle to this class as you can see req_resp.
It confuses me. What is the component host_controller_reg_memory doing. How do you activate this component. And a second thing having a component in a sequence is very unusual and I believe it is impossible. S sequence has a limited life time. It wil be created at any time and disappears when it has completed… It should be an object. And you are creating this component simply calling its constructor. This is not the common way to construct components and objects in the UVM.