In reply to ben@SystemVerilog.us:
Ben ,
A few follow up questions ::
[1] Since $stable( Sig1 ) is being used asynchronously it doesn’t inherit the Clocking event .
This is similar to using $stable in continuous assign statements
assign stableVal = ( $stable( ConfigSig , @( posedge clk ) ) ? sigVal : errorVal ;
Hence we need to specify clocking event in $stable within reject_on .
**Is my understanding correct ?**
[2] I changed the Clock Sampling to ::
reject_on( ! $stable( Sig1, @( clk) ) ) $stable( Sig1 ) s_until_with $rose( Sig2 ) ;
If I use **reject_on( ! $stable( Sig1, @( posedge clk) ) )**
it is equivalent to property_expression without using ' reject_on ' i.e
$stable( Sig1 ) s_until_with $rose( Sig2 ) ;
Hence a glitch between 2 posedge of clk would go unnoticed .
**NOTE :: Using @( clk ) a glitch between posedge N negedge OR negedge N posedge still goes unnoticed .**
[3] Since ’ reject_on ’ samples the Signals asynchronously .
My guess is this could leads to performance issues for longer simulations .
**Is usage of ' reject_on ' discouraged ?**