Issue with register access sequences

UVM
1

Hi all,
iam using the UVM register sequences to test my reg block. one of the seq “uvm_reg_access_seq” which does front door write followed by backdoor read to the reg block and vice versa. I see an issue and the backdoor reads are failing. i tried to debug it further goes deep into the DPI calls and iam unable to proceed

My seq call:

  reg_access_seq = uvm_reg_access_seq_temp::type_id::create("reg_access_seq");
  reg_access_seq.model=regmodel_obj.regmodel.axi;
  reg_access_seq.start(null,this);

UVM_ERROR /share/edasw/cadence/XCELIUM/20.12.001/tools/methodology/UVM/CDNS-1.2/sv/src/reg/uvm_reg.svh(2899) @ 121276000: reporter [RegModel] Register “regblock.axi.eth_status_fields” value read from DUT (0x00000000000101ff) does not match mirrored value (0x00000000000000ff)

the bits 8 and 16 are R/W bits with set to 1 on reset.

Any pointers are appreciated.
Thank you

2

In reply to seenu:

Did you run uvm_reg_hw_reset_seq first? It looks like there is a mismatch after reset. Check the actual register value in the RTL.

3

In reply to seenu:

The reset is not done automatically. Before doing anything you have to reset your register model like this:

regmodel.reset();
4

In reply to chrisspear:

thanks for your suggestion chris, i did run all other reg sequences and everything is working fine

5

In reply to chr_sue:

ok i will try that and let you know thank you