Issue with add_hdl_path (peeking two sub modules regsiters)

UVM
,
1

HI

I have two sub modules called A and B within DUT and trying to

get register information of both A and B in back door using peek method.

I have single ral block which includes both A and B regsiters.

I am doing in below way in env.

//A registers

m.reg_model_h.add_hdl_path(A_HIER)

regname=m_reg_model_h.get_reg_by_name(“REG_A”);

regname.add_hdl_path_slice($sformatf(“add_%0d”,0),0,5)

m_reg_model.lock_model.

//B regsiters

m.reg_model_h.clear_hdl_path(A_HIER)

m.reg_model_h.add_hdl_path(B_HIER)

regname=m_reg_model_h.get_reg_by_name(“REG_B”);

regname.add_hdl_path_slice($sformatf(“data_%0d”,0),0,5)

m_reg_model.lock_model.

module dut;

A a1;

B b1;

endmodule

When I do the peek of A regsiters I am seeing below error.

UVM_ERROR get:unable to locate hdl path test_bencg.dut.b1.add_0.

I observed that always B hierarchy overriding when accessing A regsiters. eventhough

I provided clear_hdl_path (A_HIER)

Can any one please help on this?

Thanks,

praneeth

2

In reply to praneethmspd:

You are sharing the same register model between 2 DUTs. This is finally ONE register model.
With m.reg_model_h.clear_hdl_path(A_HIER) you are removing this hdl_path from the model.
The simulator is correct …