Issue while binding structs

SystemVerilog
, ,
1

Hello,

I have a module inside my DUT which I wanted to replace with BFM. So I tried binding this particular module with my uvc interfaces at the top level. This is working except an output struct binding.
This struct is an output of that module and is driven by some child module. I am getting multiple driver error.
What I believe is binding should not throw such errors. Please find the code snippet and error

//file1

typedef struct packed
{
logic my_signal;
} my_struct;

//file2

interface my_interface(output my_struct SIGNAL_NAME);
endinterface : my_interface

//file3

module MY_CHILD_MODULE(
output my_struct SIGNAL_NAME
);
assign SIGNAL_NAME.my_signal = 1'b1;
endmodule : MY_CHILD_MODULE

//file4

module MY_MODULE(
output my_struct SIGNAL_NAME
);
MY_CHILD_MODULE my_child_module_inst(.SIGNAL_NAME (SIGNAL_NAME)); //error line. line number ERROR_LINE
endmodule : MY_MODULE

//file5

module RTL_TOP(
output my_struct SIGNAL_NAME
);
MY_MODULE my_module_inst(.SIGNAL_NAME (SIGNAL_NAME));
endmodule : RTL_TOP

//file6

module tb_top;
my_struct my_local_signal;
RTL_TOP rtl_top_inst(.SIGNAL_NAME (my_local_signal));

//here I need to replace MY_MODULE with my uvc interface, my_interface
bind MY_MODULE my_interface my_interface_inst (.SIGNAL_NAME  (SIGNAL_NAME));
endmodule : tb_top

Error which I am getting is from ERROR_LINE "Variable ‘tb_top.rtl_top_inst.my_module_inst.SIGNAL_NAME’ has multiple conflicting drivers and the indicated output port connection in scope ‘tb_top.rtl_top_inst.my_module_inst’ is contributing to this conflict set

Can some help me to understand why this elaboration error is coming?

2

In reply to rexjohn4u:

The problem is when you declare an output port using a data type, it is implicitly declared as a variable, not net type, and variables are only allowed a signal continuous assignment to them. There is already a continuous assignment from the output of MY_CHILD_MODULE, and the bind statement adds another from the output of my_interface.

To make this work, you need to change the output of MY_MODULE to a wire.

module MY_MODULE(
output wire my_struct SIGNAL_NAME
);
MY_CHILD_MODULE my_child_module_inst(.SIGNAL_NAME (SIGNAL_NAME)); 
endmodule : MY_MODULE
3

In reply to dave_59:

Hello dave_59,

Thanks for your solution. It is working like a charm.

But unfortunately in my case MY_MODULE is the rtl file which I am not supposed to change.
So I made a work around in tb_top which happens to be working.

bind MY_MODULE my_interface my_interface_inst (.*); //cause the signal names are matching

Can you please comment on this solution. Any ill effect?

4

In reply to rexjohn4u:

I don’t see why changing the port connection to .* removes the error. You still have two continuous assignments to the same variable. I still get the error in Questa.

If you cannot change the RTL, you should get the designers to change the RTL for you so you can verify their design.

5

In reply to dave_59:

I tried simulating and it seems to be working. The values I am driving from interface is getting reflected at RTL level.
I see your point. I am not sure whether its Cadence tool issue.
Let me talk to designers.

Thanks