enabled x-propagation for verifying the design(all Verilog files). my test bench files all are in system Verilog.
I am getting the errors like this “a non-pure function call”.
“a non-instrumentable system task $finish”
In design they are calling functions in case statements.
In reply to mani77:
This is a tool specific feature, please contact your tool vendor.
In reply to dave_59:
In reply to mani77:
This is a tool specific feature, please contact your tool vendor.
Thanks Dave for your reply.
sorry. those are not the errors . after running test case ,it will generate xprop.log file .
in that file ,I am facing that issues.whatever I mentioned in 1st post.
In reply to mani77:
“Enabled x-propagation” is a tool specific feature that changes the your Verilog code to simulate with behaviors outside the IEEE LRM specification. From what I have seen, different tools have varying limitations on what kind of Verilog code they support with this feature.
My personal opinion is that formal tools are now much more efficient at catching the kinds of problems you looking to find instead of dynamic simulation.