Is UVM synthesizable?

UVM
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Hey,

I am just started learning about UVM and SystemVerilog. I have a simple question about UVM. Is UVM synthesizable in a FPGA?

I would like to develop a UVM based testbench for a real electronic system. My idea was to describe the DUT as an entity with inputs and outputs connected to the FPGA’s pins. This way I can verify my real hardware design through a DUT which acts as a bridge between the testbench and my real system. But for that purpose I need to know if the developed testbench made with UVM is synthesizable in a FPGA. I have read the SystemVerilog is synthesizable (except some exceptions, same as in Verilog or VHDL) and it would be logic that UVM is synthesizable as well as it is a library for SystemVerilog essencially.

Thank you in advance,
Gorka.

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In reply to Gorka3:
The UVM is not synthesizable because it uses dynamically constructed classes,

It is possible to split portions of your UVM testbench into synthesizable pieces. But stimulus generation and functional coverage is not synthesizable.

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In reply to dave_59:

Thank you for your reply Dave. So does it exist a verification or validation methodology oriented to already fabricated embedded systems, which I would like to test its functions and responses, similar to UVM?