Is there any method in SV that can return Real Time

SystemVerilog
1

If we assign real time value to seed for randomization, then for every compile and run,we will get different randomized value.

No need to change seed value manually.

2

There is no need to do this as most simulators have an option to randomize the seed for every run. In Questa, the command line option is:

vsim -sv_seed random

It will report the seed in the transcript so that you can set it manually if you need to repeat the simulation for debugging,

3

This is a common question in Verification Methodology…

It partly arises because of the paradox of random simulation : mostly you want stability, rather than wild randomization, and you certainly want repeatability.

My best advice is: you could find a way to achieve this by calling some code at runtime that calls a function that sets a seed. However, later in your project you will realize that it does not benefit you. In particular, you will need to know the exact seed that was used (and the exact point in the simulation runtime that it was set) in order to exactly reproduce the same run, for debug. A UVM class based testbench has multiple distributed random generators to accommodate random stability in a dynamic class environment. A lot of that setup happens at time zero. If you set a seed AFTER that setup you are effectively running a simulation with two seeds, not one. The thread you overrode the seed in will use your seed but others will use a seed that was derived from the original seed. So it might be very difficult to reproduce that run. You would end up implementing a way to ‘fix’ your seed override, a way to report it so that your regression system could record it, etc, etc.

Just fast-forward the above complications and do the following:

  • generate your seed outside, from your perl script or whatever (or use a fixed seed for most runs)
  • pass that seed into the simulator where it will be used as I described above
  • store it as part of your regression run metadata (e.g. print it into a saved logfile or use it as a part of your file names)
  • allow it to be overridden from the outside in your scripting, so that at debug time you can exactly reproduce the failing run (avoiding the complications I mention above)

Our Verification Manager tools support this kind of workflow… always outside the simulator, not within the SV code.

Sorry I didn’t provide an answer for your actual question… I remember experimenting with that exact functionality some years ago. Please do some more research and I hope you come to the same conclusion as I did, that it’s the ‘wrong question’.

4

In reply to dave_59:

Thanks sir for the reply. Ya this is one of the option that is supported in all the tools.

5

In reply to gordon:

Adding 1 more dumb question here.

What if i want to run simulation where two different modules will use two different seeds? Is there a way to set the seed of each module?
I know that i can change the seed using command-line arg(this will be common for all modules).

6

In reply to Naven8:

Thanks sir for the suggestion, ya i was thinking to write some script that can extract the real time from the system and to use it in SV code. But better option is to use “vsim -sv_seed random” as said by dave_59 above and this is mostly preferred for seeding.

7

In reply to arvind kumar:

Naven8,

The UVM uses a global seed, and then creates a global hash table of string pathnames used to re-seed objects. You could do a similar think using module pathnames.