For running uvm test, we have 3 steps : compilation → elaboration → simulation.
Compilation will do syntax checks and its fine.
The elaboration will make the hierarchical connections and both design and env is generated and stored in the memory as per my understanding.Is my understanding right ?
Untill we done with the compilation and elaboration we will not go for simulation right ?
3)Next is simulation of the stuff. Once we give command run -all,the simulation will start.My question is : in this simulation only the run_test in top module is called.upon the call of run_test in top module,the build phase or connect phase is triggered. BUt how the uvm env is generated in elaboration state of simulator ? what is the link between the elaboration by simulation and the build phase of UVM?
In reply to muralikrishna229:
The SystemVerilog is defined such that all classes get dynamically constructed when running a simulation. There are no statically elaborated classes.
The compilation → elaboration → simulation are steps for a tool that interprets SystemVerilog code. Theoretically, a tool knows nothing about the UVM; it’s just SystemVerilog code that happens to have a package of classes. The elaboration step of a tool does construct module instances and make hierarchical connections, but does not construct any classes. Only static variables inside class are constructed.
When you give the “run” command to start the simulation, that starts the execution of all static variable initializations, and will eventually start the initial block that contains the call to uvm_pkg::run_test() task. The run_test() task begins to sequence through its phases, starting with the build_phase that constructs the uvm_test component, which then constructs the uvm_env component, and then all the components below it. It then proceeds to execute the next phase. What may be confusing is some of the names of the UVM phases overlap terminology used by the tool. You could be more explicit by referring to the “static elaboration” step if a tool versus the UVM’s “dynamic elaboration” build phase.