Is there any difference between assertion and checkers?

SystemVerilog
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3

In reply to dave_59:

hai dave_59, thank you.

After a quick google search,

  1. I have studied that we can implement the checkers in the class.
  2. if checkers contain one or more assertions then is it correct to write these checkers in class?
  3. I know that assertions are not used inside a class because of the dynamic nature of the class.
    please correct me if am wrong in any way