In reply to vickyvinay:
Checkers are containers/building-blocks with special rules structured similar to how assertions use sequences and properties as containers. Checkers usually contain one or more assertions, so that is one big difference there. Checkers have features mainly devised for formal verification. This relatively new feature of SystemVerilog hasn’t obtained widespread adoption yet, so it’s hard find material on it.
Assertions rely on expressions evaluating true or false, which are one-bit values. It’s up to you to write boolean expressions that resolve to 1-bit (like equality), or iterate over the bits.