Is there a way to use SVA property's local variable value to be used outside property

SystemVerilog
3

In reply to ben@SystemVerilog.us:

Thanks Ben,

Thanks for solution.

I did actually thought to use verbosity feature, but used it like this


property scl_clk_per;
    realtime start_time,start_time_temp;
    realtime period;
     disable iff(!reset)
     @(posedge scl_in) (1,start_time = $time) ##0 @(negedge scl_in) ##0 (1,start_time_temp = start_time) ##0 @(posedge scl_in) (1,period = ($time - start_time_temp),`uvm_info("CLK_PERIOD",$psprintf("Actual Period =%0d",period),UVM_MEDIUM)) ##0 (period >= 1us)
 endproperty
 
clock_freq_prop : assert property (scl_clk_per) else $display("Assertion Error");

But it gives compilation error like below.

** Error: (vlog-13069) ** while parsing macro expansion: ‘uvm_info’ starting at
** at I2cIf.sv(823): near “begin”: syntax error, unexpected begin.