Is there a way to get some sort of handle to actual module if its path in string format is available?

SystemVerilog
1

I have a class structure where hierarchical paths to certain modules are present as string. It works fine with uvm_hdl_deposit and uvm_hdl_read. However to call any tasks/functions present in those modules the path in string format cannot be used. Is there a way to get to the module hierarchy from this ?

2

In reply to PANKAJ GAUR 93:

See Updated Example Code from DVCon Paper: The Missing Link: The Testbench to DUT Connection | Verification Academy and

https://verificationacademy.com/cookbook/abstractconcreteclassconnections

You can use the same principle of calling pure virtual methods to call any task in your module/interface