Is there a way to declare an enum variable for the process state?

SystemVerilog
1

Fine-grain process control in SystemVerilog has the following definition.

class process;
   typedef enum { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED } state;
   static function process self();
   function state status();
   ......
endclass

How to declare an enum variable with the state type? I tried the code below, but it doesn’t work.

process :: state my_process_state;

My purpose is to display the status of a process in a waveform.

2

You need to explain what doesn’t work means. The following works for me:

module top;
  
  process::state st;
  
  initial $display("State: %s",st.name);
  
endmodule
3

Thanks, Dave. I am using the simulator from another vendor, not Siemens. This is probably a bug in their tools.

4

Works with 3 other tools on EDAPlayground, Contact your tool vendor.