Is there a problem with connecting analysis ports, exports, implementations via direct assignment?

UVM
,
1

Let’s say we have a UVM monitor instantiated inside of a UVM agent and we want to connect the analysis ports as shown in the image below:

Normally to connect these two, I would do the following in the connect_phase() of the agent:


my_agent_ap.connect(my_uvm_monitor.my_monitor_ap);

But in someone’s code I see him/her doing this:


//export port on monitor to the agent

my_agent_ap = my_uvm_monitor.my_monitor_ap;

It seems to work. I would rather that they do the former connection method. Are there any downsides to do the later method?

2

In reply to michael_g1:

The question is not ‘it seems to work’. Some Simulator versions are tolerating Things which are not compliant with the Standard, like semicolon after a macro. With a new version ist is not tolerating this at all. For this reason: follow the rules!!! And this is the using the connect statement:

my_agent_ap.connect(my_uvm_monitor.my_monitor_ap);