Is modport necessary

SystemVerilog
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1

I have read a lot about modports on various sites, but I am not clear on how exactly they help restrict access in an interface where signals are inout by default. My understanding is only at this basic level - we don’t want both TB and DUT driving a signal inside the interface, leading to an “x”.

Two questions, please help :

  1. Do I really need modports?
  2. Simple explanation of the “need for modports”.

Thanks

2

In reply to UVM_learner6:

See modports: Aside from the definition of ins, outs, and inouts you can include setup and hold times. See my reply at Do we use modport of an interface when connecting to UVM test? | Verification Academy
Ben systemverilog.us