In reply to resnathomas:
Verilog will allow you to assign a strong0 to a tri1 signal. I don’t know USB well enough to know if this works for you. Note that you cannot model the current sensing ports of USB in Verilog - that is for analog simulation.
In reply to resnathomas:
Verilog will allow you to assign a strong0 to a tri1 signal. I don’t know USB well enough to know if this works for you. Note that you cannot model the current sensing ports of USB in Verilog - that is for analog simulation.