Is it possible to pulldown a tri1 signal

SystemVerilog
3

In reply to dave_59:

Hi Dave,

In my testbench I have declared ‘dp’ port(in usb protocol) as tri1 net. But I want to pull down the port to simulate a usb BC SDP. If I use a pulldown, there will be a contention which will lead to x. So can I use a strong signal to assign to it?

Thanks in Advance!