In reply to srikanthvvs1:
Hi,
I’m working on validating an IP which has AXI as main interface. TB has two different sequencers one for AXI read channel and one for AXI write channel to drive txns independently.
So, i want reg model to select appropriate rd_sequencer or wr_sequencer based on whether its a read access or write access. is this possible ?
should i create two different reg maps one for read and one for write and do connections as below or is there a better way?
axi_reg_blk.rd_reg_map.set_sequencer(rd_sequencer,rd_adapter);
axi_reg_blk.wr_reg_map.set_sequencer(wr_sequencer,wr_adapter);
The key question is if your UVM architecture is correct. You need only 2 agent when you have a dual-port memory.
Is this really the case?