Is it possible to let two instances to generate same sequence of random numbers?

SystemVerilog
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1

Hi All,

I have a class that generates 10 random numbers. And in the test program, I create two instances c1 and c2. I wonder if it is possible to let c1 and c2 generate the same sequence of number? That’s to say, if c1 generates 7,8,3,2,5,1,4,0,9,6, I wonder if it is possible to let c2 also generates 7,8,3,2,5,1,4,0,9,6?
I tried to use srandom() to set the initial seed, but it seems to have no effect on the result.

class c_rng;
  int i;
  task gen_print();
    repeat(10)begin
    	i=$urandom;
    	$display("i=%0d",i);
    end
  endtask
endclass

module test;
  c_rng c1,c2;
  initial begin
    c1=new();
    c2=new();
    c1.srandom(1);
    c2.srandom(1);
    $display("c1 generates");
    c1.gen_print();
    $display("c2 generates");
    c2.gen_print();
  end
endmodule

Thanks in advance for your help!

Hao

2

In reply to peterjin:
$urandom uses the process RNG, not the class RNG. Change $urandom to randomize and your code works.

class c_rng;
  rand int i;
  function void gen_print();
    repeat(10)begin
      void'(randomize());
    	$display("i=%0d",i);
    end
  endfunction
endclass

module test;
  c_rng c1,c2;
  initial begin
    c1=new();
    c2=new();
    c2.set_randstate(c1.get_randstate());
    $display("c1 generates");
    c1.gen_print();
    $display("c2 generates");
    c2.gen_print();
  end
endmodule

I prefer to use the RNG from c1 to set the RNG of c1. You don’t want to get involved managing seeds and master seeds.

3

In reply to dave_59:

Thanks so much for your help!