Is it possible to create parameterized class with arg as array?

SystemVerilog
,
1

Hi,

I am trying to create an parameterized class and one of the arg is array. Is it legal to pass an array?


class abc #(int size, int arr[]);

int arr_size = size;
int array[] = arr;

endclass

//creating object
arr[] = {4,5,6};
abc #(3, arr) abc_h;

//getting error
The parameter override should be an expression containing only constant 
  numbers and previously defined parameters.
2

In reply to UVM_SV_101:

The error message told you exactly what is wrong. You were trying to pass arr as a parameter when it’s declared as a variable. Change the declaration of arr to a parameter.

parameter int arr[] = {4,5,6};