Is it necessary to build reg model in uvm to simulate with xilinx IPs?

UVM
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1

In our project, we have used several Xilinx IPs that work together with our custom modules. The Xilinx IPs contain more than 100 registers. When using UVM simulation, we need to configure these registers in the IPs through the AXI Lite bus.

In this situation, we might need to create a register model similar to the code below. However, is there a way to directly read and write to these registers by manipulating their addresses and thereby avoid creating this reg model?



`ifndef REG_MODEL__SV
`define REG_MODEL__SV

class reg_invert extends uvm_reg;

    rand uvm_reg_field reg_data;

    virtual function void build();
        reg_data = uvm_reg_field::type_id::create("reg_data");
        // parameter: parent, size, lsb_pos, access, volatile, reset value, has_reset, is_rand, individually accessible
        reg_data.configure(this, 1, 0, "RW", 1, 0, 1, 1, 0);
    endfunction

    `uvm_object_utils(reg_invert)

    function new(input string name="reg_invert");
        //parameter: name, size, has_coverage
        super.new(name, 16, UVM_NO_COVERAGE);
    endfunction
endclass

class reg_model extends uvm_reg_block;
   rand reg_invert invert;

   virtual function void build();
      default_map = create_map("default_map", 0, 2, UVM_BIG_ENDIAN, 0);

      invert = reg_invert::type_id::create("invert", , get_full_name());
      invert.configure(this, null, "");
      invert.build();
      default_map.add_reg(invert, 'h9, "RW");
   endfunction

   `uvm_object_utils(reg_model)

    function new(input string name="reg_model");
        super.new(name, UVM_NO_COVERAGE);
    endfunction 

endclass
`endif
2

In reply to designer007:

or some simple way to generate this reg model

3

In reply to designer007:

However, is there a way to directly read and write to these registers by manipulating their addresses and thereby avoid creating this reg model?

For sure you can, e.g. you can define the registers addresses as macros and develop your own API methods to generate read/write transactions on any required address, but I believe using the UVM register model is much more simpler.

or some simple way to generate this reg model

The different EDA vendors provide utilities to save your time and helps you in the generation of the register models, e.g. Questa provides Register Assistant package.

With these utilities, you will just need to write down the registers specification in an abstract format (varies according to the used utility) and the utility converts it to UVM register model.