Is Interface in system verilog synthesizable?

SystemVerilog
1

INterfaces can be instantiated in the design.
The design can be converted to netlist. What happens to the signals declared in an interface.
Are they converted into Gate LevelNetlist?

2

In reply to Curious_cat:

Yes, most synthesis tool can handle interfaces. Check your tool before proceeding further. They usually get expanded out into the module they are instantiated in.

3

You also should check your entire tool chain. Your simulator and synthesis tools will support it, your formal equivalency tool will probably support it, but you might still hit restrictions if you are also targeting an emulation platform.

4

In reply to warnerrs:

Thank you for your response.