Is $dumpvars(0, <some_top>); supposed to dump all submodules and signals under <some_top> in Questa 10.4?

SystemVerilog
,
1

Hi,

I have a test bench that has a top that has the following code in it to dump all vars in the top module.

initial begin
  $dumpfile("dump.vcd");
  $dumpvars(0, top.atop);
end

atop is a module w/:

module apb_top(
  clk,
  rst,...
);
  b i_b(.clk(clk),.rst(rst));
endmodule

module b(
  clk,
  rst
);
  a i_a(.clk(clk),.rst(rst));
endmodule

module a(
  clk,
  rst
);
endmodule

The resulting dump.vcd though only show the signals of atop. The instance i_b is there too but no signals. Module a is not shown in i_b.

Please help me with this issue.

Thanks,
Martin

2

In reply to Martin John H. Borja:
$dumpvar has levels: This argument specifies the levels of hierarchy, consistent with the corresponding argument to the $dumpvars system task (see 1800-2012 section 21.7.1.2). If this argument is not specified, it defaults to 0 (i.e., the specified module and in all module instances below the specified module). Example:

$dumpvars (1, top); // Because the first argument is a 1, 
// this invocation dumps all variables within the module top;
// it does not dump variables in any of the modules instantiated by module top.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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3

Hi Ben,

Thanks to your reply.
I am also using the same verilog LRM.
The fix though to my problem is tool specific.
For Questa, there is a flag that must be set during compilation to acceess the sub modules and ports in the top design.
This is entirely different in other tools.

Thanks,
Martin