Is char a keyword in system verilog

SystemVerilog
1

Hi,

Had this question is character a datatype in system verilog like in C? I saw that being used in a blog but when I used it to write code in edaplayground it is not being highlighted as keyword and giving error.
I am trying to randomize a string and was using array of char for that.

Here is my code:

class str_random;
string str;
rand int str_length;
rand char c;

constraint a1 { str_length inside {[6:9]};}
constraint a2 { c.size() == str_length;
foreach(c[i]) {
c[i] inside {[65:90]};
}
}
constraint a3 { solve str_length before c;}

             function void post_randomize();
             foreach(c[i]) begin
               str = {str,string'(c[i])};
             end
             endfunction

endclass

module try;
str_random ss;

initial begin
ss = new();
ss.randomize();
$display(“the string is: %s”, ss.str);
end
endmodule

Error-[SE] Syntax error
Following verilog source has syntax error :
variable type is not user defined type
“testbench.sv”, 7: token is ‘c’
rand char c;

Thanks!

2

In reply to curious_verifier:

Appendix B of the IEEE 1800-2017 SystemVerilog LRM (plus all versions of the LRM) list the legal set of keywords and char is not one of them.

I believe there are 2 reasons for SystemVerilog using byte instead of char.

  1. From a hardware design language perspective, a byte is more descriptive for its purpose
  2. At the time SystemVerilog was invented, the size of char was dependent on locale (UTF-8/16, UCS-1/2). But today it is pretty much fixed at 8-bits.
3

Thanks Dave for confirming on that. I didn’t find in LRM and wanted to double check on forum.