Is bind usage limited to assertions/checkers/monitors only

SystemVerilog
,
1

Hello ,

Is it possible to use bind to override an existing rtl module with a tb/vip component.

The below code attempts to do the same and we see multiple driver issues with it.

Any help or work around is appreciated.



//   Actual DUT RTL
module rtl(
		      input wire       clk,reset,
		      input wire [1:0] req,
		      output wire [1:0] gnt);
 
   assign gnt = 1;
endmodule


//  overide tb componenet

module override_rtl(input wire clk_ip, reset_ip,input wire  [1:0] req_ip, output wire [1:0] gnt_ip);
   assign gnt_ip = 3;
endmodule

module rtl_tb();

   reg reset,clk = 0;
   reg [1:0]  req = 0;
   wire [1:0] gnt;

   parameter OVERIDE = 1;
   

   always  #3  clk ++;

   initial begin
      reset <= 1;
      #20  reset <= 0;
      // Make the assertion pass
      #100  @ (posedge clk) req  <= 2;
   
   end

   generate 
      if(OVERIDE) begin : overide
	 bind rtl_tb   override_rtl     overide_inst (
							// .vip port (RTL port)
							.clk_ip   (clk),
							.req_ip   (req),
							.reset_ip (reset),
							.gnt_ip   (gnt)
							);
      end
   endgenerate
   rtl rtl_inst (clk,reset,req,gnt);

endmodule
2

Bind is just a shortcut for instantiating a module form outside the scope of where you want it to be placed. The same connection rules apply as if you had explicitly instantiated the module inside the target scope. So inevitably you will run into more issues with ports that try to add drivers to existing signals.

Your example would work if you changed the continuous assignment to

assign (supply0,supply1) gnt_ip = 3;

which overpowers the existing drivers on the wire. That will work when you bind a port to a wire, but not to variables.

However a better solution is to use the library configuration mechanisms in your tool to select which version of a module you want to use, or the Verilog configuration construct directly. Either way, the way tools manage libraries is tool specific and you should consult the documentation.