Invalid X or Z in state expression value for constraint

UVM
,
1

Hi,

I am facing an error “Invalid X or Z in state expression value for constraint” with modelsim 10.3a questa in below sequence. I have confirmed that there is no any x or z value assigned in constraint list.

Can you please let me know how can I resolve this issue OR how can I debug it further with modelsim?

sequence snippet :-

task generateFrame;
begin
forever
  begin
   frameGenerationEvent.wait_trigger(); 
    int i;
    integer identifier;

    identifier = prevFrame.BaseId2;

    /* randomizing field with below constraint */ 

    //auto-constraints
    `uvm_do_on_with (this.trans,p_sequencer.agentSeqr,{
    FrameKind  == DATA;
    FrameFormat== prevFrame.FrameFormat;  
    Dlc        == prevFrame.Dlc;
    Data.size  ==  prevFrame.Dlc;
    foreach (Data[i]) Data[i] == prevFrame.DataToDut[i];
    Identifier == identifier; 
    }) 
 end
end

Thanks in advance!

Best Regards,
Maulik Vyas

2

The error message should have included a line number that points to the constraint in question. Usually the problem is a confusion over which scope a variable in the ‘with’ constraint is referring to.

Also, there is no need to declare int i in your task, and you should use int to declare identifier instead of integer if you really do not ever want to see an X.

3

In reply to maulik_87:

What are the data types associated with prevFrame? It is recommended that you use 2-state data types for all UVM objects. I’m thinking that you have some four state data types that are either uninitialized or set to X or Z.

4

In reply to dave_59:

Hi Dave,

 I am hitting the same issue, where I want to deliberately drive x's on a signal as per the specification and I want the x's driven on input-2 only for certain values of input-1. How can I achieve this ?

I declared the variables in the sequence as rand logic and randomizing the seq item using the “with” construct.

How can I drive x’s using some constraints? Is logic type not allowed to be used in constraints ? If yes, why is this restriction ?

Thanks,
Madhu

5

In reply to mseyunni:

There are a couple of reasons for this restriction, but the main is is the SystemVerilog language is not defined well enough to propagate X’s very well, which in turn makes it very difficult to define a constraint solver around X’s.

Consider initializing a register with X’s and having an expression that XORs or subtracts itself. Real hardware will always produce zero, but since Verilog has no way to correlate an X from one signal with the same X from another signal, it pessimistically can only produce another X. And there are many ways that an X can be optimistically converted to a 1 or 0 because of the way the signal gets propagated: (4-state to 2-state assignment, conditional branches taking the false or default branch).

We suggest you look at the application of formal tools to deal with unknowns instead of dynamic event driven simulation.

If you still want to deliberately drive an X using random stimulus, you can either create an extra random bit variable or add an extra bit to an existing random variable and drive your X by looking at that bit in post_randomize()