Invalid type for net: Error

SystemVerilog
,
2

In reply to Bhaskar44:

With what you have shown, you don’t need a wire. You can use a continuous assignment to a variable of any type, as long as there is only one continuous assignment driving the variable.

module test()
       real dut_volt;
       assign dut_volt = dut.voltage;
endmodule

If you need multiple drivers to the same signal, then you have to use a wire and a wire with anything beyond an integral data type needs a special declaration. See 6.7.2 Net declarations with user-defined nettypes in the 1800-2012 LRM for more information.

BTW, please use code tags when posting your code.