To whom it may concern: I have been asked to learn OVM and take the OVM class. After viewing a few classes, the instructor refers to things I know nothing about. Such as classes, packages, constrictors, ect. I have looked for a class on introduction to system Verilog and I don’t see one. The classes I see that involve system Verilog seem to be for someone who is already versed in system Verilog. My level of Verilog is the following… I know what an always block is, a combinatorial statement, and can instantiate lower level modules. And that’s about it. Is there a system Verilog class within the courses offered by the verification academy that can teach someone system Verilog who has no experience beyond what I listed above?
Thank you.