In reply to ben@SystemVerilog.us:
Hello Sir, Thank you so much for the explanation.
Still, I think the last question requires special attention. That question emphasizes that if sig_b appears, it should not be more than one clock cycle. It’s not appearing, that’s acceptable; and if it intends to show up, it should be for one clock cycle. We need to focus on this one clock cycle factor.
That’s why I came up with that solution. I admit the first repetition was unnecessary. To be honest, thinking about it now, I believe it’s stupidity.
!a |-> b[=0:1] ##1 a;
- I think this one is perfect.
If there is any more suitable answer, please put it in this thread. And also, please look into my observation. b[=0:1] takes care of the number of occurrences of sig_b. Now the reason behind using a non-repetition operator instead of using a goto one is we don’t know when a will be asserted after the occurrence of b if it happens.