Interview Questions on Assertions

SystemVerilog
,
13

In reply to ben@SystemVerilog.us:

Hi, I was just observing your solution. And I think, I got another way to write an assertion for Question:- 05.


// Question - If there are two occurrences of sig a rising with state=ACTIVE1, 
// and no sig b occurs between them, then within 3 cycles of the second rise of sig a, START must occur.
    property p1;
    $rose(a) && state == ACTIVE1 ##1 !b[*1:$] ##1 $rose(a) && state == ACTIVE1 |-> [1:3]state == start;
    endproperty
    assert property (p1);

Could you tell me whether I can do it or not?