Interview question on constraint

SystemVerilog
, ,
4

In reply to burra thanuja:

There are many ways to do this, one way is to use the post randomization.

module abc;
  
  class aa;
    rand int unsigned val[10];
 
    constraint s1 {
      foreach(val[i]){
        val[i] < 10;
        foreach(val[j]){
          if(i < 9 && j < 9 && i != j)
            val[i] != val[j];
        }
      }
    }
    
     function void post_randomize();
        val[10] = val[$urandom_range(0,8)];
     endfunction
          
  endclass

 initial begin
    aa a1 = new();
    a1.randomize();
    $display(a1.val);
  end

endmodule
2 Likes