Interview question on constraint

SystemVerilog
, ,
2

In reply to burra thanuja:

module abc;
  class aa;
    rand int unsigned val[10];
    
    constraint s1 {
      foreach(val[i]){
        val[i] < 10;
        foreach(val[j]){
          if(i != j)
            val[i] != val[j];
        }
      }
    }	
  endclass
          
  initial begin
    aa a1 = new();
    a1.randomize();
    $display(a1.val);
  end
endmodule

this is the way to generate the unique values with out using unique keyword