Hi,
I am performing a Gate Level Simulation of a design.I used Virtex 7 as the Device.My DUT is in Verilog and test bench is in UVM.
I ran “Generate Post-Place & Route Simulation Model” to generate timsesim.v and .sdf files.
I brought this files in to questasim and tried to run it with UVM testbench.
I used “Simprims” and “Unisims” Libraries.
But I am getting some error
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle \s_t_0/div_sel_tip_AND_47_o in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle \s_t_0/ss_sel_tip_AND_58_o_0 in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle \s_t_0/tx_sel[3]_wb_we_i_and_42_OUT<0> in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle \s_t_0/ss[2]_wb_dat_i[2]_MUX_112_o in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle \s_t_0/ss[4]_wb_dat_i[4]_MUX_110_o in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle \s_t_0/ss[5]_wb_dat_i[5]_MUX_109_o in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle \s_t_0/ss[7]_wb_dat_i[7]_MUX_107_o in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle \s_t_0/ss[8]_wb_dat_i[8]_MUX_122_o in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle mmso_IBUF_4403 in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle mmsi in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle N2 in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle N4 in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle N6 in du my_top(<anon>)
# Internal Error: do_merge_inst_toggle_data: can't find inst toggle N8 in du my_top(<anon>)
N2,N4,N6,N8 are all wires created by Xilinx in the Gate Level file.There are many errors like this.
I tried to simulate the design without the sdf file.Then also it is showing the same error.
So I think I didnt include some library while simulating…I dont know which library to be included.
Any body knows how to solve this issue???