I would like to configure my Verilog DDR2 controller with QVIP provided DDR2 Memory(TLM) as an AHB slave and test it with AHB master sequences from the AHB example. I have an interface to convert AHB address to DDR2 address space and have implemented the AHB Slave functionality in the Controller.
At the interface, I want to verify both the AHB Slave functionality and the controller functionality of the DDR2 Controller.
Could anyone point me to how to use two VIPs in the same environment?
Thank you