Interfacing VHDL DUT to UVM

UVM
1

Hi

I have a small VHDL IP block and i am trying to build a UVM compliant test bench to valiadate it.

My question is: My IP block is written in VHDL. How do i interface this IP block to the UVM test bench?

One though i had was to build a SystemVerilog wrapper to wrap the VHDL IP block and to use TLM ports to interface this wrapper to the UVM sequencer/driver. Is this a sensible approach?
Any othr approaches ?

Thanks in advance

JO

2

Hi Jao16,

A wrapper is a good idea in this case.

You should have a look at the compile switch “-mixedsvvh” if you are using Questa.
This will allow you to use VHDL-Constructs inside of your SV code.

I hope this helps.

Bye,

Frodus

3

Hello

Can anyone point me to examples of building a System Verilog TLM based wrapper for the VHDL DUT? ( Iam not even sure if the wrapper needs TLM compatible ports.)

The DUT interface consists of two split transaction bus ports:
a) A host processor makes a read/write request to memory. This request is formatted and then sent to memory (host makes 32-bit read/write requests, whilst the memory is 24-bits wide, with four banks)

    b) the read requests are split transaction -  the host makes the read request and some time later the memory returns the read data (in-order). This 24-bit data is then buffered into 32-bit chuncks and then returned to the host processor.

Currently i am modeling four interface ports to the DUT
a) Host read/write request port
b) Memory read/write request port
c) Memory returning read data port
d) Host receiving read data.

Thanks in advance.

JO

4

Hi Jao,

I think a TLM interface is not needed for this. When I got it correct I TLM interfaces are needed for communication inside of the UVM parts.
But I guess yo are more looking into a DUT which is written in VHDL and Interfaces connected to this.
If that is correct then I would generate a SystemVerilog wrapper around your VHDL DUT like this:

// A short example which I've not compiled:
module vhdl_dut_wrapper (
  write_if.DUT write_if,   // You should define SV-Interfaces for each logical VHDL group
  read_if.DUT read_if
  input clk, reset)

  vhdl_dut (
     .clk(clk),
     .write_data(write_if.data),
     .write_addr(write_if.addr)
     ....
  );
endmodule

This wrapper can now be directly placed inside of your TB and you can connect the different
agent-drivers to it.

I hope this helps a bit.

Bye,

Frodus

5

Hi Fordus

THanks for the tips.

I will give it a go.

Thanks and regards

JO