In reply to srbeeram:
Another way to think of this is that design units (modules, interfaces and packages) are just ways of creating containers of behaviors. As long as the behaviors are synthesizable, it should not matter how these behaviors get connected together.
However, SystemVerilog has rules about how you compose/elaborate a design. There has to be at least one top-level module, and that module creates dependancies on other design units by instantiating other modules and interfaces, connecting interface ports, and importing packages. Those dependancies create recursive dependancies and that determines what is needed to elaborate the full design for simulation or synthesis.
The original intent of an interface was simply a defined set of port connections that would be connected through module ports. But over time, more module like-features got added in making the distinction less obvious.