In reply to srbeeram:
We cannot have only interfaces, even if they can encapsulate whatever a module will encapsulate. During SYNTH you still need a module as a wrapper to run SYNTH efficiently.
On top of that while running SYNTH since interfaces are used on the PORT declaration, since they are as per definition a simple collection of wire, always/ff/comb blocks used internally are not captured by the SYNTH tool resulting into an empty module (with ports)
interface uuiif (
input logic clk,
input logic reset,
input logic d,
output logic q
);
always_ff @(posedge clk or posedge reset) begin
if(reset) q <= '0;
else q <= d;
end
endinterface
module p(uuiif iif);
endmodule
Using Mentor Precision you will get:
module p ( \rtlc_iif.clk , \rtlc_iif.reset , \rtlc_iif.d , \rtlc_iif.q ) ;
input \rtlc_iif.clk ;
input \rtlc_iif.reset ;
input \rtlc_iif.d ;
output \rtlc_iif.q ;
endmodule
This instead would work but TOOLS could complain (for instance I found Mentor interprets async reset as CLK stating that there is a multi-clocked block).
// Code your design here
interface uuiif (
input logic clk,
input logic reset,
input logic d,
output logic q
);
task ff;
if(reset) q <= '0;
else q <= d;
endtask
endinterface
module p(uuiif iif);
always_ff @(posedge iif.clk) begin
iif.ff;
end
endmodule
Hope this clarifies. Regards