Hi
In System Verilog the recommended approach to create interfaces is through modport
suppose I have an interface like
*interface axi_if(input clk, input rst);
logic arlen;
clocking mclk@(posedge clk);
output arlen;
endclocking
modport Master(clocking mclk, input clk, input rst);
endinterface*
In Bind we can bind a module to an interface if all the ports are in the portlist.
So is there someway I can bind arlen though it is not defined in the interface port list?
You can always create continuous assignments to patch things together after you bind in the interface, but that will become very cumbersome. Can you explain why you need to use bind? And can you explain how you expect to drive the clocking block?
In reply to dave_59:
Hi Dave,
This is, lets say, for white box testing. I want to bind the interfaces of some sub-module and write assertions and protocol checkers. This will be a monitor clocking block and hence no driving of the clocking block.
In reply to justrajdeep:
Typically, the interfaces or modules that you use in a bind have ports for all the signals you want to attach via the bind. Why do you not want to do that?
In reply to dave_59:
But in my case the interface is defined by someone else (at a central library). I am not at liberty to change it. On the other hand I can create a local copy, that beats the whole purpose of having one interface file and everyone using it.
In reply to justrajdeep:
You really need to shoe a lot more code with some attempts at what you want to do. Another suggestion is to wrap the interface inside another interface or module, and bind that module or interface instead.
module axi_if_wrapper(input clk, rst, arlen);
axi_if itf(.*);
assign itf.arlen = arlen;
endmodule