Interface issue

SystemVerilog
5

In reply to vybhava:

If you want to share signals in one interface with another interface, make them ports of the interface. You need to use wires if you want to have bidirectional signals.

interface mem_ctrl_if (
    input logic Reset,  // shared signals
    input logic Clock
  );
  logic [9:0] Addr; // per interface instance signals
  wire [7:0] Data;
  logic RWn;
endinterface

interface mem_if(
    input logic reset,
    input logic clock
  );
  logic enable;
  logic [7:0] addr;
  wire [7:0] data;
  logic rwn;
endinterface

Then when you instantiate them

mem_if mem0if(ctrl_if.Reset,ctrl_if.Clock);