In reply to John Verif:
John,
I have modified the ram controller code and made it working. I came to following conclusion on interface and modport usage.
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In interface declaration if direction(input, output and inout) is not defined only way to connect is using assign statement. If direction is declared we can connect during instantiation.
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If interface has modport we can not use modport instance to connect the signals wia port. We have to use assign statement to connect interface signals then modport of same interface should be passed to respective modules. Please refer to below code. Modport is passed to all the modules.
Please note → Still I need to figure out how to handle the inout data.
I used the VCS simlator.
mem_ctrl_if.sv
interface mem_ctrl_if ();
logic Reset;
logic Clock;
logic [9:0] Addr;
logic [7:0] Data;
logic RWn;
modport mem_ctrl_md (input Reset,Clock,Addr,RWn,inout Data);
endinterface
mem_if.sv
interface mem_if();
logic reset;
logic clock;
logic enable;
logic [7:0] addr;
logic [7:0] data;
logic rwn;
modport mem_md(input reset, clock, enable, addr, rwn, inout data);
endinterface
ram.sv
module RAM (mem_if.mem_md MemBus);
logic [7:0] mem[0:255];
always @ (negedge MemBus.reset or posedge MemBus.clock or MemBus.enable)
begin
if (MemBus.enable)begin
if (~MemBus.reset)
//MemBus.data = 8’bz;
$display(“Need to add the code\n”);
else begin
if (MemBus.rwn)
//MemBus.data = mem[MemBus.addr];
$display(“Need to add the code\n”);
else
mem[MemBus.addr] = MemBus.data;
end
end
end
endmodule
mem_ctrl.sv
module mem_ctrl(mem_ctrl_if.mem_ctrl_md ctrl_if);
logic [3:0] Enable;
//instantiate interfaces
mem_if mem0if();
assign mem0if.reset = ctrl_if.Reset;
assign mem0if.clock = ctrl_if.Clock;
assign mem0if.enable = Enable[0];
assign mem0if.addr = ctrl_if.Addr[7:0];
assign mem0if.data = ctrl_if.RWn ? 8'bz : ctrl_if.Data;
assign mem0if.rwn = ctrl_if.RWn;
mem_if mem1if();
assign mem1if.reset = ctrl_if.Reset;
assign mem1if.clock = ctrl_if.Clock;
assign mem1if.enable = Enable[1];
assign mem1if.addr = ctrl_if.Addr[7:0];
assign mem1if.data = ctrl_if.RWn ? 8'bz : ctrl_if.Data;
assign mem1if.rwn = ctrl_if.RWn;
mem_if mem2if();
assign mem2if.reset = ctrl_if.Reset;
assign mem2if.clock = ctrl_if.Clock;
assign mem2if.enable = Enable[2];
assign mem2if.addr = ctrl_if.Addr[7:0];
assign mem2if.data = ctrl_if.RWn ? 8'bz : ctrl_if.Data;
assign mem2if.rwn = ctrl_if.RWn;
mem_if mem3if();
assign mem3if.reset = ctrl_if.Reset;
assign mem3if.clock = ctrl_if.Clock;
assign mem3if.enable = Enable[3];
assign mem3if.addr = ctrl_if.Addr[7:0];
assign mem3if.data = ctrl_if.RWn ? 8'bz : ctrl_if.Data;
assign mem3if.rwn = ctrl_if.RWn;
//Enable Memory based on [9:8] bits at Addr
assign Enable[0] = (ctrl_if.Addr[9:8] == 2'b00) ? 1'b1 : 1'b0;
assign Enable[1] = (ctrl_if.Addr[9:8] == 2'b01) ? 1'b1 : 1'b0;
assign Enable[2] = (ctrl_if.Addr[9:8] == 2'b10) ? 1'b1 : 1'b0;
assign Enable[3] = (ctrl_if.Addr[9:8] == 2'b11) ? 1'b1 : 1'b0;
//instantiate RAMs
RAM ram0 (.MemBus (mem0if.mem_md));
RAM ram1 (.MemBus (mem1if.mem_md));
RAM ram2 (.MemBus (mem2if.mem_md));
RAM ram3 (.MemBus (mem3if.mem_md));
endmodule
tb.sv
module tb;
mem_ctrl_if CTRL_IF();
mem_ctrl U_mem_ctrl(CTRL_IF.mem_ctrl_md);
endmodule
In cpu code there is problem, Following usage is wrong.
cpu_if cpuif(); // This instance already has ram_if, rom_if and alu_if. You can use this as cpuif.rom_if, cpuif.alu_if and cpuif.rom_if
cpuif.ram_if ramif(); // Wrong
cpu_if.ram_if ramif(): // Correct usage
cpuif.rom_if romif(); // Wrong
cpuif.alu_if aluif(); // Wrong
Please past the complete code of CPU.
Lets continue the discussion if concepts are not clear.
Thanks
Vybhava S