Interface is static or dynamic?

SystemVerilog
1

Hi ,

Can you please tell whether Interface in systemverilog is static or dynamic?

regards,

sharat

2

In reply to SHARAT KOTTUR:

SystemVerilog module, interface, and package all comes under category of modules with more or less advantages of ‘module’ construct. And that’s why interface is static.

3

In reply to SHARAT KOTTUR:
The short answer to your short question is that interfaces are statically allocated by may be dynamically referenced.

I assume you are asking this question because you have seen the term “virtual interface” and you are wondering if it has an effect on how interfaces get allocated. It does not. Modules and interfaces are instantiated by the compiler. The module and interface hierarchy and their ports usually get flattened out (or in-lined) by the elaboration process, along with resolving hierarchical references.

SystemVerilog does not have pointers that allow you to dynamically reference different static objects, but an exception was made in the case of interface instances. A virtual interface variable can be dynamically set with a path to different actual interface instances. That allows you to dynamically reference members of an interface instance.