Interface and driver component of Dual Port RAM is not working properly

In reply to ASHISH PATEL:

Did you put my code change into the interface, replacing the always() block? In the driver, you want to do simple assignments to the interface logic variables.


  virtual task run_phase(uvm_phase phase);
    dpram_seq_item req_rand; 
      forever begin
        seq_item_port.get_next_item(req_rand);
        `DRV_IF.address_0  = req_rand.address_0;
        `DRV_IF.cs_0       = req_rand.cs_0;
        `DRV_IF.we_0       = req_rand.we_0;
        `DRV_IF.oe_0       = req_rand.oe_0;
        `DRV_IF.data0      = req_rand.data0;
        `DRV_IF.address_1  = req_rand.address_1;
        `DRV_IF.cs_1       = req_rand.cs_1;
        `DRV_IF.we_1       = req_rand.we_1;
        `DRV_IF.oe_1       = req_rand.oe_1;
        `DRV_IF.data1      = req_rand.data1;
        @posedge(`DRV_IF.clk); 
        seq_item_port.item_done();
        $display("Here are the randomized values at driver\n");
        req_rand.print();
        $display("Value of data_0 = %0h",`DRV_IF.data_0);
        $display("Value of data_0 = %0h",req_rand.data0);
     end
  endtask:run_phase