Questasim will compile a file assuming that the language extension is correct. Since the file is named with a .v extension, pure Verilog is assumed. The ‘-sv’ compilation option will tell the compiler that the file contains SystemVerilog and the extension is ignored.
If you use the Questasim Project Manager, you need to right click on the file and tell Questasim to use SystemVerilog instead of the default language syntax.
However, in this case, renaming the file with a .sv extension is probably a good thing to do, so there is no issue doing what you did.