In reply to verif_25:
yes as I said in my previous reply Only the name of the module and the memory ports are different ( mem_* I/O ). All other features are identical (APB, Power, BIST, Redundancy, etc.)
below you can see both interfaces, I hope I provided all the needed infos
interface memory_wrapper_rw_if#(
parameter MODE = “ASIC” ,
parameter MEM_NB_WORDS = 32 ,
parameter MEM_SIZE_WORDS = 8 ,
parameter APB_ADDR_WIDTH = 6 ,
parameter ENABLE_ECC = 0 ,
parameter ENABLE_APB = 1 ,
parameter ENABLE_LATCH = 0 ,
parameter ASIC_ENABLE_BIST = 1 ,
// Inputs
logic rst_n_i;
logic mem_wr_clk_i ;
logic mem_wr_rst_n_i ;
logic mem_wr_ena_i ;
logic [$clog2(MEM_NB_WORDS)-1:0] mem_wr_add_i ;
logic [MEM_SIZE_WORDS-1:0] mem_wr_ben_i ;
logic [MEM_SIZE_WORDS-1:0] mem_wr_dat_i ;
logic mem_rd_clk_i ;
logic mem_rd_rst_n_i ;
logic mem_rd_ena_i ;
logic [$clog2(MEM_NB_WORDS)-1:0] mem_rd_add_i ;
logic [MEM_SIZE_WORDS-1:0] mem_rd_dat_o ;
logic pwr_halt_i ;
logic pwr_rdy_o ;
logic core_clk_i ;
logic core_rst_n_i ;
logic apb_pclk_i ;
logic apb_prst_n_i ;
logic [APB_ADDR_WIDTH-1:0] apb_paddr_i ;
logic apb_psel_i ;
logic apb_penable_i ;
logic apb_pwrite_i ;
logic [7:0] apb_pwdata_i ;
logic apb_pstrb_i ;
logic apb_pready_o ;
logic [7:0] apb_prdata_o ;
logic apb_pslverr_o ;
logic test_ena_i ;
logic test_scan_i ;
/////////////////////////////////////////////////////////////////////
interface memory_wrapper_2rw_if#(
parameter MODE = “ASIC” ,
parameter MEM_NB_WORDS = 32 ,
parameter MEM_SIZE_WORDS = 8 ,
parameter APB_ADDR_WIDTH = 6 ,
parameter ENABLE_ECC = 0 ,
parameter ENABLE_APB = 1 ,
parameter ENABLE_LATCH = 0 ,
parameter ASIC_ENABLE_BIST = 1 ,
// Inputs
logic rst_n_i;
[b]logic mem_a_clk_i ;
logic mem_a_rst_n_i ;
logic mem_a_ena_i ;
logic mem_a_rdwen_i ;
logic [$clog2(MEM_NB_WORDS)-1:0] mem_a_add_i ;
logic [MEM_SIZE_WORDS-1:0] mem_a_wr_ben_i;
logic [MEM_SIZE_WORDS-1:0] mem_a_wr_dat_i;
logic [MEM_SIZE_WORDS-1:0] mem_a_rd_dat_o;
logic mem_b_clk_i ;
logic mem_b_rst_n_i ;
logic mem_b_ena_i ;
logic mem_b_rdwen_i ;
logic [$clog2(MEM_NB_WORDS)-1:0[b]] mem_b_add_i ;
logic [MEM_SIZE_WORDS-1:0] mem_b_wr_ben_i;
logic [MEM_SIZE_WORDS-1:0] mem_b_wr_dat_i;
logic [MEM_SIZE_WORDS-1:0] mem_b_rd_dat_o;
logic pwr_halt_i ;
logic pwr_rdy_o ;
logic core_clk_i ;
logic core_rst_n_i ;
logic apb_pclk_i ;
logic apb_prst_n_i ;
logic [APB_ADDR_WIDTH-1:0] apb_paddr_i ;
logic apb_psel_i ;
logic apb_penable_i ;
logic apb_pwrite_i ;
logic [7:0] apb_pwdata_i ;
logic apb_pstrb_i ;
logic apb_pready_o ;
logic [7:0] apb_prdata_o ;
logic apb_pslverr_o ;
logic test_ena_i ;
logic test_scan_i ;