In reply to chr_sue:
Hello thank you for your answer.
I’ll try to detail more : so basically in my design I have the two following verilog files : “memory_rw.v” for single core memory (holding memory_rw top level module ) and an other file called “memory_2rw.v” which holds the memory_2rw module.
as I said these two are two independent top level modules that I need to verify.
my question is about how to verify them in my testbench : should I instantiate both modules in a single testbench module or should I create two different top testbench modules in for each .
same question for the DUT interfaces.
I hope now it is more clear for you.
Thanks.