In reply to chr_sue:
we distinguish 1R1W 2P memories ( but it is not a dual port mem as we can not perform for example 2 write Operations simultaneously in both ports) and 2RW DP memories.
Anyway thanks for your help so far , I’ll try to figure it out myself as I don’t think that we are converging as my question is not related to how many clocks or resets I have.
my question is a general one and I wanted to know what is the best practice when we have such design with many top level modules with some common pins.