In reply to chr_sue:
Thanks for reply chr_sue. Could you please share some more knowledge about SoC verification and Virtual sequencer concept.
Can you explain me or share documents or links about virtual sequencer in detail. I have some questions and want to get detail idea about below queries. Please help me out
Why we use virtual sequencer ??
what is virtual sequencer and virtual sequence??
how can we control multiple sequences in test bench using virtual sequencer or virtual sequence??
if we can control using two components(virtual sequencer & virtual sequence) can you tell me difference between virtual sequencer and virtual sequence??
what is the difference between virtual sequence/virtual sequencer to non virtual sequence/non virtual sequencer???
When we are writing directed test cases how can we control multiple env/tests in test bench??